Abstract - This Multiscale Integration of Manufacturing and Assembly Processes (MIMAP) demonstration project investigates the integration of two or more Thrust Area Groups (TAGs) by creating a flow of information and processes from two areas of research. The control theory research of two different controllers for diffusion furnaces used in semiconductor manufacturing which predict a specific window of machine failure, the mean-time-before-failure (MTBF).

The objective is to increase yield, decrease cycle time, work-in-progress (WIP) and production costs. A global factory Minimum Inventory Variability Scheduling policy (MIVP^®) [8,9], used to decrease cycle time and cycle time variance when compared to a first-in-first-out (FIFO) scheduling policy, was used to make the comparisons between the two inner and outer loop controllers.

The project's Cross Cutting Methodologies (CCMs) is ensured by the participation of faculty from three different colleges (LAS, CEAS, and CTAS) and two electrical engineering doctoral students.

I. INTRODUCTION

This project investigates the impact caused by the variability of machine breakdowns (MTBF) using a standard Proportional-Integral-Derivative (PID) controller with a FIFO scheduling policy, comparing it to a new H^∞ controller [4,5,7,11,13,19] using a FIFO scheduling policy and then making the same comparisons replacing the FIFO scheduling policy with the MIVP^® 1-Step Ahead scheduling policy**.

The actual implementation of MIVP^®** scheduling policies has been successful in reduction of cycle time within three semiconductor FABs from 25% to 45% and in reducing variance as much as 95% [9,10]. MIVP^® simulation experiments in many semiconductor factory (FAB) models has achieved results of an average cycle time reductions of 40%. The MIVP^® algorithm and FAB specific customized rules compare the next process step buffers (queues) with the historical average of those same buffers when calculated over time using FIFO as baseline scheduling policy.

II. SIMULATION SCENARIOS

The project uses a discrete event stochastic simulation model, which has been validated to meet the Kempf Specification** of the five machine six buffer problem [7,8,17,19] shown in Figure 1. The simulation software platform of Extend^® + Manufacturing from Imagine That, Inc.* in addition to Extend^® + Semiconductor Manufacturing** from ACADZ, inc. was used to develop the model scenarios.

Figure 1. Schematic diagram of the 5 machines 6 steps process flows

The Kempf Dataset (see Figure 1.) of the five machine six buffer Mini-FAB discrete event simulation model was used to make the comparisons [6,14,16]. The Diffusion Bay (Cell 1), consisting of, two parallel machines in the six-step process flow for the manufacturing of two products (Pa & Pb) and test wafers (TW), includes the process simulator with PID and H^∞ controllers in place of historical Mean Time Between Failures. The mean-time-to-repair (MTTR) was fixed as a normal distribution of 24 hours with a standard deviation of 1 hour for all comparisons. Preventive Maintenance (PM) was scheduled according to the Kempf specification [6] for all comparisons. Batching of three lots was done for the two diffusion machines according to specification. The Implant Bay (Cell 2) containing two parallel machines was not altered. It contained the historical emergency maintenance of MTBF and MTTR and scheduled PM as per specification. The Photo Bay (Cell 3) with only one machine having only PM for one case, and PM and setup's for another were also according to specification.

The project required ten (10) runs to collect the necessary statistics to calculate a 95% confidence interval in the results. Each run covering a time-period of two years of production with the first one-half year removed for simulation model ramp-up bias. This gave a total of 20 years of data with the first five years removed for ramp-up bias. Cycle time (CT), work-in-progress (WIP), machine queues, product input, product output, and machine utilization’s statistical data were recorded [11].

The production run scenarios are listed as follows:

Table 1. Production Run Scenarios

Run #1. To calculate the FIFO work-in-progress (WIP), theoretical cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B No MTBF No MTTR No PM

Cell 2 Machines C & D No MTBF No MTTR No PM

Cell 3 Machine E No MTBF No MTTR No PM

Note: There is no difference for MIVP^® theoretical cycle time and machine utilization.

Run #2. To calculate the FIFO work-in-progress (WIP), theoretical cycle time and machine utilization’s with aconstant release of one (1) lot (48 wafers/lot) every 120 minutes and Setup’s for different Steps and products

Cell 1 Machines A & B No MTBF No MTTR No PM

Cell 2 Machines C & D No MTBF No MTTR No PM

Cell 3 Machine E No MTBF No MTTR No PM

Note: There is no difference for MIVP^® theoretical cycle time and machine utilization.

Run #3. To calculate the FIFO work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B PID MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #4. To calculate the FIFO work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B H^∞ MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #5. To calculate the MIVP^® work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B PID MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #6. To calculate the MIVP^® work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B H^∞ MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

For Run #7 through Run #10, repeat Runs #3 through Run #6 by having setup’s for Machine E as specified in Table 4 (Set-Up Times Map for Machine E) with “Constant release of one (1) lot (48 wafers/lot) every 120 minutes”.

Table 2. Kempf Five Machine Six Buffer Mini-FAB Specification

Number of Machine Groups	3
Semiconductor Operations	Diffusion	Implant	Photo
Manufacturing Cells	Cell 1	Cell 2	Cell 3
No. of Machines/Group	2	2	1
Number of Job Types	3
Number of Tasks/Job	6	6	6
Job Types (products)	Pa	Pb	TW
Distribution Function of Job Types	0.60	0.36	0.04
Constant Mean Inter-arrival Time of Jobs	2 hrs.	120 mins.
Length of the Simulation	730 days	17120 hrs.	1051200 mins.
Ramp-Up Bias	182.5 days	4380 hrs.	262800 mins.
Number of Shifts per Day	2 shifts	12 hrs. each
Lot Size - wafers	48
Start Buffer	Infinity
Controllers	PID	H^∞
Schedulers	FIFO	MIVP®

Table 3. Cell Layout

Start	starts in warehouse	far left end	buffer = infinite
C1	Ma & Mb	left	buffer max = 18 lots
C3	Me	center	buffer max = 12 lots
C2	Mc & Mb	right	buffer max = 12 lots
Out	outs to warehouse	far right	buffer = infinite

Table 4. Production management for 3 products

Process Flow and Machine Groups in Route

Job Type	S1	S2	S3	S4	S5	S6	out
Pa in	1	2	3	2	1	3	out
Pb in	1	2	3	2	1	3	out
TW in	1	2	3	2	1	3	out

Product Production Flow

Job Type	S1	S2	S3	S4	S5	S6	out
Cells	C1	C2	C3	C2	C1	C3	out
Machines	Ma	Mc	Me	Mc	Ma	Me	out
Machines	Mb	Md		Md	Mb		out

Mean Service Time (in minutes) for successive tasks

Job Type	S1	S2	S3	S4	S5	S6
Pa	225	30	55	50	255	10
Pb	225	30	55	50	255	10
TW	225	30	55	50	255	10

Mean Load Time (in minutes) for successive tasks

Job Type	S1	S2	S3	S4	S5	S6
Pa	20	15	10	15	20	10
Pb	20	15	10	15	20	10
TW	20	15	10	15	20	10

Mean Unload Time (in minutes) for successive tasks

Job Type	S1	S2	S3	S4	S5	S6
Pa	40	15	10	15	40	10
Pb	40	15	10	15	40	10
TW	40	15	10	15	40	10

Tot Service Time = Load + Unload + Process Times

Job Type	S1	S2	S3	S4	S5	S6
All Products	285	60	75	80	315	30

Set-Up Times Map for Machine E

Present Step	Previous Step	Setup According To Type	Setup Time Minutes
S3	S3	same	0
S3	S3	Different	5
S3	S6	same	10
S3	S6	Different	12
S6	S3	same	10
S6	S3	Different	12
S6	S6	same	0
S6	S6	Different	5

III. COMMENTS ON FURNACE CONTROL

The process under consideration is silicon oxidation taking place in a batch furnace [13,15,17,20]. The control objective for this wafer-processing problem is to manipulate the control inputs in order to achieve accurate and repeatable growth of silicon oxide on the wafers. The kinetics of the process are approximately given by the Deal-Grove model

y’ = (2y + B(T))^-1A(T)

where y’ is the derivative of y with respect to time, y denotes the oxide thickness (Å) and T is the temperature (°K). The parameters A(T) and B(T) have an Arrhenius dependence on temperature.

To improve processing uniformity across the boat, common industrial furnaces have 3-7 heating zones, each one associated with a separate heating element and a thermocouple to measure the temperature. Temperature controllers rely on such measurements to adjust the power applied to each heating element. Mathematical models of such a process can be derived from heat and mass transfer balances and takes the form of nonlinear partial differential equations. Alternatively, one can use input-output data to fit the temperature response of the furnace by a linear (or nonlinear), finite-dimensional, dynamical systems [18]. The latter approaches, used here, yield models that are valid only locally for an operating condition but are relatively simple. The obtained models allow excellent prediction of the closed-loop response.

The model used in this example describes an industrial furnace with three heating zones and has the form

T = G(s)[sat(q)]

where T is the vector of temperatures and q is the vector of powers across heating zones. G(s) is a MIMO (Multiple Inputs Multiple Outputs) transfer matrix describing the basic dynamics and zone-interactions of the heating process and sat(× ) denotes a saturation non-linearity.

Figure 2. Schematic description of an industrial furnace

Translated into a temperature control problem, the objective is to follow a desired temperature trajectory prescribed by a “recipe”. This recipe is derived from a preliminary characterization of the furnace and aims to achieve a trade-off between processing time and uniformity/repeatability of the processed wafer properties. Temperature control is commonly implemented using single-loop PID controllers while more advanced model-based multivariable controllers have recently begun to appear. Although their differences in terms of their performance in the given application are not the subject of the present work, they are both used to expose the advantages of tight “inner-loop” control in the process results.

The main obstacle to achieving the above control objective is attributed to “external disturbances,” that describe, in a cumulative fashion, the effects of unmodeled components of the process. Such components can be separated into two categories: those that are “repeatable” and those that are not (i.e., “random”). For example, repeatable errors are produced by parameter mismatch in the kinetic model, introduction of reactant gases in the flow, etc. These errors occur at specific instants in a given recipe; and their effects are fairly independent of the time that the process starts. On the other hand, “random” perturbations are caused by measurement noise, pressure drops in the reactant lines due to the operation of other processes, etc. The overall simulation results retain the qualitative characteristics of actual processes.

Regarding the perturbations, four contributions are considered, each emulating a type of perturbation appearing in actual processes:

1. A deterministic disturbance at the heating power. This has the form of a filtered step function at the beginning of the oxidation process and its purpose is to emulate the temperature loss due to the introduction of cold reactant gases.

2. A deterministic disturbance at the thermocouple. This has the form of a slow drift (0.004 deg/run) and its purpose is to emulate thermocouple drift due to fouling. Effectively, this perturbation causes the thickness of the deposited oxide to grow until it exceeds a prescribed tolerance and thus initiating a maintenance cycle. The thickness change due to temperature offset has a slope of 4.3 Å/deg. For nominal operation (8 runs/day), this translates into an increase of the maintenance window by 7 days for every one Å increase of the range of variation of the thickness.

3. A stochastic disturbance at the heating power. This has the form of a band-limited, filtered white noise and aims to emulate low frequency perturbations (e.g., valve activity of MFC’s). For this disturbance, amplitude changes occur once every 10 min.

4. A stochastic disturbance at the heating power. This has the form of a band-limited, filtered white noise and aims to emulate higher frequency perturbations (e.g., pressure drop due to valve activity of other processes).

It should be emphasized that, although physically motivated, these disturbances, as well as the kinetic constants and tolerance specifications, are not entirely realistic in terms of their amplitude. Certain effects are exaggerated for two reasons. One is to speed-up the simulation and the other is to capture variability caused by other sources. Still, the temperature responses are reasonable approximations of reality: The simulated steady-state error is ±1 degree compared to an actual figure of ±0.2-0.5 degrees. Moreover, process results show a variability of about 0.5 Å across the boat and between runs compared to an actual figure of 3-5 Å.

Finally, the recipe used for this example is as follows:

1. 0-15 min: 50 deg. ramp-up and stabilization period. No reaction occurs.

2. 15-approx. 215-min: Set-point temperature control, reactant gas flow and reaction activity. The reaction end-point is determined during the reactor characterization (clean thermocouples!) to achieve the desired mean thickness.

3. 215-265 min: Inert gas flow and cool-down period.

Again, recipes for actual processes would involve longer ramp-up and ramp-down periods but since no reaction takes place doing these steps, they are shortened for the sake of simplicity.

Two controllers are used to execute the above recipe. One is a multivariable robust controller designed using an

H^∞ approach to minimize sensitivity subject to robustness constraints. This design, uses a model and uncertainty estimates computed from real data, and is a simplified version of a controller implemented in the furnace [20]. The corresponding closed-loop bandwidth is 6 rad/min. The other controller is a decoupled PID tuned to a closed-loop bandwidth of 0.5 rad/min. For this furnace, this represents a “detuned” PID, and it is selected to emphasize the benefits of tight “inner-loop” control. (The actual bandwidth achieved by decoupled PIDs in this case is about 2 rad/min.) The difference between the two controllers is unambiguously demonstrated by the temperature responses and the process results. While the high frequency perturbations are naturally attenuated by the low-pass nature of the process, the processing time is too short to achieve an effective averaging of the low-frequency perturbations. For the latter, the attenuation provided by the high-performance H^∞ controller is an order of magnitude better than the detuned PID. Accordingly, the steady-state temperature error with the H^∞ is about an order of magnitude lower than the PID. This also translates into a variance of thickness across the boat and between runs that is an order of magnitude better with the high-performance temperature controller, as an be seen in Figures 3 and 4. The implication of this result is that tight inner-loop control reduces the process variance and allows for a more reliable and repeatable prediction of the maintenance times. In turn, this can be exploited by an advanced scheduling algorithm to minimize the cycle time and its variance. (The improved repeatability in the process output is another advantage but it is not explored any further in this study.)

In approximate quantitative terms, letting dy denote the thickness half-range (variability ±dy, in Å) and dL denote the threshold of tolerance around the nominal thickness (in Å),

Maintenance (Failure) Window = dy/(0.004*4.3) runs

MTBF = dL/(0.004*4.3) runs

under the assumption that 8 runs are performed each day. From the preliminary simulations, the above relationships suggest the following performance characteristics for each controller:

Table 5. Performance characteristics for each controller

Controller	Thickness Range	Failure Window
PID	±0.8 Å	±46.5 runs (6 days)
H^∞	±0.06Å	±3.5 runs (0.4 days)

The MTBF for both controllers is the same with value of 116.3 runs (14.5 days).

IV. DESCRIPTION OF THE STEPS TO OBTAIN THE FAILURE PROBABILITY FUNCTIONS FOR THE SIMULATIONS

The recipe for each controller (PID and H^∞) was obtained for the nominal case when there were no input-disturbance and no output measurement drift presented in the system.

Under these conditions, the specified average thickness objective of 480Å is achieved with processing times of 197.84 minutes and 195.98 minutes for the PID and H^∞ controllers, respectively.

The processing time does not include the ramp-up and ramp-down time needed, it corresponds only to the time described in step 2 of the recipe.

In order to obtain the failure probability functions for a given desired tolerance (±2Å), and output measurement drift, 120 different realizations for the input disturbance were used to produce a histogram of occurrences of various thickness. With this histogram, it is possible to approximate the probability of failure for a given thickness.

For small drifts (up to the tolerance), the histograms obtained for different values is the same and from this the probability function can be calculated.

In Figure 5 and Figure 6 the failure probability function are shown for the different inner loop controllers.

Figure 3. Resulting thickness after 200 min processing across zones

For simplicity, we assume that the same failure probability function for a given controller is valid for both processing steps, Step 1 and Step 5, although the processing time for these steps is different.

The time scale for the probability of failure function is given in terms of successfully completed steps or runs. This time scale is the intermediate step among the real time scale used by the controller for each machine and the discrete event time scale used by the two scheduling policies, FIFO and MIVP^®.

V. RESULTS

The comparison of the mean cycle time among different strategies (selection for the scheduling policy and low-level controller for “cell 1”) is shown for each product and for the average between the products.

Case 1, no setup’s for Machine E:

· For a given scheduling policy (FIFO or MIVP^®) there is always improvement when the H^∞ controller is used instead of the PID controller.

· For a given low-level controller (H^∞ or PID) the overall performance of MIVP^® is better than that obtained with the FIFO policy. This overall improvement is achieved by a detriment in the performance for Product A and a better performance for the other two products.

Figure 4. Temperature response of the two controllers for the 200 min processing recipe (both simulations contain an offset of 800 deg)

Figure 5. PID controller probability of failure

Figure 6. H^∞ controller probability of failure

Case 2, setup’s for Machine E:

· In this case, the MIVP^® scheduling policy is outperformed (marginally) by the FIFO scheduling policy. The reason for this result is that the MIVP^® scheduling policy does not make explicit use of the fact that there are setup’s.

· For a given scheduling policy (FIFO or MIVP^®) there is always improvement when the H^∞ controller is used instead of the PID controller.

It is important to stress the fact that local variance has a strong impact on the higher level control structure hierarchy as can be seen in the results obtained for the H^∞ and PID controllers. It is shown by Little’s Law and Kingman’s Formula that, to reduce the mean cycle time, variability must be reduced [1,2]. There are many variability sources that can affect cycle time. The two addressed in this paper deal with the variability of emergency maintenance, the inner loop (H^∞ and PID controllers), and the variability of resource scheduling, the outer loop (FIFO or MIVP^®).

In Table 7 and 8, the results obtained for the sets of simulations are presented.

VI. ACKNOWLEDGMENT

This project was supported by the Intel Corporation, Motorola, Inc., ACADZ inc., the College of Engineering and Applied Sciences and the Department of Manufacturing Engineering Technology of Arizona State University East, Mesa, Arizona. Thanks to proof reader Bill Cocoran.

* Extend^® + Manufacturing is a registered trademark of Imagine That, Inc.

** MIVP^® and MIVP^® 1-Step Ahead are registered trademarks of ACADZ, Inc.

*** Kempf model specification is provided by Dr. Karl Kempf, Intel Corporation for University research.

VII. REFERENCES

1. J. D. C. Little, “A Proof of the Queueing Formula: L=lW,” Operations Research, Vol. 9, 1961, pp. 383-387.

2. Leonard Kleinrock, Queueing Systems, Vol. 1, John Wiley & Sons, New York, NY, 1975.

3. S. Li, T. Tang, and D.W. Collins, “Minimum Inventory Variability Schedule with Applications in Semiconductor Fabrication,” IEEE Transaction on Semiconductor Manufacturing, Vol. 9, No. 1, February 1996, pp. 145-149.

4. El Adl, A.A. Rodriguez, and K.S. Tsakalis, “Modeling and Control of Re-entrant Semiconductor Manufacturing Lines: A Hierarchical Approach, Proceedings of the 1996 Conference on Decision and Control, Kobe, Japan.

5. El Adl, J.J. Flores, M. Kawski, A.A. Rodriguez, K.S. Tsakalis, “Hierarchical Modeling and Control of Re-entrant Semiconductor Fabrication Lines,'' Proceedings of the 1997 American Control Conference, Albuqurque, NM, Invited Session.

6. K. Kempf, “Detailed Description of Multiple Product Re-entrant Semiconductor Manufacturing System Example,” Prepared report, Intel Corporation, Technology, and Manufacturing Group, August, 1994.

7. T.S. Cale, P.E. Crouch, L. Song, and K.S. Tsakalis, “Optimal Control for LPCVD,” Proc. Symposium on Process Control, Diagnostic and Modeling in Semiconductor Manufacturing, The Electrochemical Society, Vol. 95-2, 97--107, Reno, May 1995.

8. D.W. Collins, K. Williams, and F.C. Hoppensteadt, “Implementation of Minimum Inventory Variability Scheduling 1-Step Ahead Policy in a Large Semiconductor Manufacturing Facility,” 6th Annual IEEE International Conference on Emerging Technologies and Factory Automation, UCLA, Los Angeles, Sept 9-12, 1997.

9. D.W. Collins and F.C. Hoppensteadt, “Investigation of Minimum Inventory Variability Scheduling Policies in a Large Semiconductor Manufacturing Facility,” 1997 American Control Conference, Albuquerque, New Mexico, June 4-6, 1997.

10. D.W. Collins and B.G. Zaslavsky, “A Numerically Effective Optimization Technique for Scheduling Time Varying Production Flows in Semiconductor Manufacturing”, INFORMS 1996 Conference, Atlanta Georgia, November 3-6, 1996.

11. J.J. Flores-Godoy, Y. Wang, D.W. Collins, F.C. Hoppensteadt, and K. Tsakalis, “Intel Mini-FAB Simulation Model comparing machine scheduling polices of FIFO with MIVP^® with constant release policy and using a PID controller and H^∞ controller for the diffusion bay for apriori maintenance.” Presented at the SSERC Seminar of Multiscale Integration of Manufacturing and Assembly Processes, October 17, 1997, ASU.

12. F.C. Hoppensteadt, Analysis and Simulation of Chaotic Systems, Springer-Verlag, New York, 1993.

13. K.S. Jun, D.E. Rivera, K.S. Tsakalis, H.M. Liaw, E. Hall, and C. Stein, “PID Optimization for Temperature Control of Epitaxial Growth,” Proc. ECS Conference, 373--374, Montreal, Feb. 1997.

14. K. Kempf, Detailed description of a two-product, six-step five-machine re-entrant semiconductor manufacturing system, prepared report, Intel Corporation, Technology & Manufacturing Group, August, 1994.

15. J.J. Kristoff, L.J. Song, K.S. Tsakalis, and T.S. Cale, “Optimally Controlled Programmed Rate Deposition of Tungsten,” VLSI Multilevel Interconnect Conference, Santa Clara, CA, June 1997

16. .N. Srivatsan, and K. Kempf, “A linear programming model of a re-entrant system, prepared notes,” Intel Corporation, Technology & Manufacturing Group, July, 1994.

17. K.D. Stoddard, P.E. Crouch, M. Kozicki, and K.S. Tsakalis, “Application of Feed-Forward and Adaptive Feedback Control to Semiconductor Device Manufacturing,” Proc. American Control Conference, 892--896, Baltimore, 1994.

18. K.S. Tsakalis, and P.A. Ioannou, Linear Time-Varying Systems: Control and Adaptation. Prentice-Hall, Englewood Cliffs, New Jersey, 1993.

19. K.S. Tsakalis, J.J. Flores-Godoy, and A. A. Rodriguez, “Hierarchical Modeling and Control of Re-Entrant Semiconductor Fabrication Lines: A Mini-Fab Benchmark,” Proc. 6th IEEE Int. Conference on Emerging Technologies and Factory Automation, Los Angeles, Sept. 1997, pp. 508-513.

20. K.S. Tsakalis, and K.D. Stoddard, “Integrated Identification and Control for Diffusion/CVD Furnaces,” Proc. 6th IEEE Int. Conference on Emerging Technologies and Factory Automation, Los Angeles, Sept. 1997, pp. 514-519.

[a] Summation of all processing time for each step plus the time needed for batching

	Products Ave.	Product Pa	Product Pb	Product TW
PID Mean Cycle Time, FIFO	4134.0±88.3	4155.1±90.8	4858.7±85.3	3388.1±96.0
H^∞ Mean Cycle Time, FIFO	3462.4±23.5	3499.4±14.6	4194.1±25.3	2693.5±60.4
PID Mean Cycle Time, MIVP^®	3899.3±62.6	4176.7±75.5	4605.4±63.4	2915.7±63.3
H^∞ Mean Cycle Time, MIVP^®	3373.8±22.3	3519.4±16.0	4082.1±30.9	2520.0±45.8
Raw Processing Time[a]	1277.915±0.909	1277.915±0.909	1277.915±0.909	1277.915±0.909
TQT[b], PID FIFO	2856.1235	2877.2493	3580.8557	2110.2656
TQT, H^∞ FIFO	2184.5004	2221.5628	2916.255	1415.6834
TQT, PID MIVP^®	2621.3977	2898.8603	3327.5275	1637.8051
TQT, H^∞ MIVP^®	2095.9532	2241.5301	2804.1914	1242.1381
PID Mean WIP[c], FIFO	39.20±2.18	23.23±1.73	15.03±1.50	0.933±0.373
H^∞ Mean WIP, FIFO	29.83±1.60	17.40±1.19	11.56±1.17	0.866±0.343
PID Mean WIP, MIVP^®	36.40±1.56	22.86±1.76	12.36±1.54	1.166±0.671
H^∞ WIP, MIVP^®	29.16±1.23	16.66±0.805	11.90±0.897	0.600±0.219

	Products Ave.	Product Pa	Product Pb	Product TW
PID Mean Cycle Time, FIFO	4955.3±118.6	4980.0±118.0	5665.4±126.4	4220.5±119.1
H^∞ Mean Cycle Time, FIFO	4048.4±35.4	4745.8±43.9	3301.4±53.3	3301.4±53.3
PID Mean Cycle Time, MIVP^®	4967.9±120.2	5291.1±114.8	5800.2±127.6	3812.4±132.8
H^∞ Mean Cycle Time, MIVP^®	4530.0±72.9	4705.5±85.7	5411.4±71.4	3473.1±77.7
Raw Processing Time	1287.167±1.007	1287.167±1.007	1287.1679±1.007	1287.1679±1.0076
TQT, PID FIFO	3668.2	3692.922	4378.2588	2933.4191
TQT, H^∞ FIFO	2761.3068	3458.6406	2014.2434	2014.2434
TQT, PID MIVP^®	3680.7645	4003.9635	4513.0724	2525.2576
TQT, H^∞ MIVP^®	3242.8846	3418.3908	4124.2796	2185.9833
PID Mean WIP, FIFO	44.10±1.79	25.46±2.48	16.93±1.52	1.70±0.62
H^∞ Mean WIP, FIFO	36.03±2.29	20.30±1.83	14.56±1.08	1.16±0.40
PID Mean WIP, MIVP^®	45.70±2.15	27.33±1.90	17.30±1.50	1.06±0.38
H^∞ WIP, MIVP^®	42.30±0.92	25.83±1.20	15.00±0.88	1.46±0.65

I. INTRODUCTION

II. SIMULATION SCENARIOS

III. COMMENTS ON FURNACE CONTROL

PID

IV. DESCRIPTION OF THE STEPS TO OBTAIN THE FAILURE PROBABILITY FUNCTIONS FOR THE SIMULATIONS

V. RESULTS

VI. ACKNOWLEDGMENT

PID Mean Cycle Time, FIFO

PID Mean Cycle Time, FIFO