Abstract - This Multiscale Integration of Manufacturing and Assembly Processes (MIMAP) demonstration project investigates the integration of two or more Thrust Area Groups (TAGs) by creating a flow of information and processes from two areas of research. The control theory research of two different controllers for diffusion furnaces used in semiconductor manufacturing which predict a specific window of machine failure, the mean-time-before-failure (MTBF).

The objective is to increase yield, decrease cycle time, work-in-progress (WIP) and production costs. A global factory Minimum Inventory Variability Scheduling policy (MIVP^®) [8,9], used to decrease cycle time and cycle time variance when compared to a first-in-first-out (FIFO) scheduling policy, was used to make the comparisons between the two inner and outer loop controllers.

The project's Cross Cutting Methodologies (CCMs) is ensured by the participation of faculty from three different colleges (LAS, CEAS, and CTAS) and two electrical engineering doctoral students.

I. INTRODUCTION

This project investigates the impact caused by the variability of machine breakdowns (MTBF) using a standard Proportional-Integral-Derivative (PID) controller with a FIFO scheduling policy, comparing it to a new H^∞ controller [4,5,7,11,13,19] using a FIFO scheduling policy and then making the same comparisons replacing the FIFO scheduling policy with the MIVP^® 1-Step Ahead scheduling policy**.

The actual implementation of MIVP^®** scheduling policies has been successful in reduction of cycle time within three semiconductor FABs from 25% to 45% and in reducing variance as much as 95% [9,10]. MIVP^® simulation experiments in many semiconductor factory (FAB) models has achieved results of an average cycle time reductions of 40%. The MIVP^® algorithm and FAB specific customized rules compare the next process step buffers (queues) with the historical average of those same buffers when calculated over time using FIFO as baseline scheduling policy.

II. SIMULATION SCENARIOS

The project uses a discrete event stochastic simulation model, which has been validated to meet the Kempf Specification** of the five machine six buffer problem [7,8,17,19] shown in Figure 1. The simulation software platform of Extend^® + Manufacturing from Imagine That, Inc.* in addition to Extend^® + Semiconductor Manufacturing** from ACADZ, inc. was used to develop the model scenarios.

Figure 1. Schematic diagram of the 5 machines 6 steps process flows

The Kempf Dataset (see Figure 1.) of the five machine six buffer Mini-FAB discrete event simulation model was used to make the comparisons [6,14,16]. The Diffusion Bay (Cell 1), consisting of, two parallel machines in the six-step process flow for the manufacturing of two products (Pa & Pb) and test wafers (TW), includes the process simulator with PID and H^∞ controllers in place of historical Mean Time Between Failures. The mean-time-to-repair (MTTR) was fixed as a normal distribution of 24 hours with a standard deviation of 1 hour for all comparisons. Preventive Maintenance (PM) was scheduled according to the Kempf specification [6] for all comparisons. Batching of three lots was done for the two diffusion machines according to specification. The Implant Bay (Cell 2) containing two parallel machines was not altered. It contained the historical emergency maintenance of MTBF and MTTR and scheduled PM as per specification. The Photo Bay (Cell 3) with only one machine having only PM for one case, and PM and setup's for another were also according to specification.

The project required ten (10) runs to collect the necessary statistics to calculate a 95% confidence interval in the results. Each run covering a time-period of two years of production with the first one-half year removed for simulation model ramp-up bias. This gave a total of 20 years of data with the first five years removed for ramp-up bias. Cycle time (CT), work-in-progress (WIP), machine queues, product input, product output, and machine utilization’s statistical data were recorded [11].

The production run scenarios are listed as follows:

Table 1. Production Run Scenarios

Run #1. To calculate the FIFO work-in-progress (WIP), theoretical cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B No MTBF No MTTR No PM

Cell 2 Machines C & D No MTBF No MTTR No PM

Cell 3 Machine E No MTBF No MTTR No PM

Note: There is no difference for MIVP^® theoretical cycle time and machine utilization.

Run #2. To calculate the FIFO work-in-progress (WIP), theoretical cycle time and machine utilization’s with aconstant release of one (1) lot (48 wafers/lot) every 120 minutes and Setup’s for different Steps and products

Cell 1 Machines A & B No MTBF No MTTR No PM

Cell 2 Machines C & D No MTBF No MTTR No PM

Cell 3 Machine E No MTBF No MTTR No PM

Note: There is no difference for MIVP^® theoretical cycle time and machine utilization.

Run #3. To calculate the FIFO work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B PID MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #4. To calculate the FIFO work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B H^∞ MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #5. To calculate the MIVP^® work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B PID MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

Run #6. To calculate the MIVP^® work-in-progress (WIP), cycle time and machine utilization’s with a constant release of one (1) lot (48 wafers/lot) every 120 minutes

Cell 1 Machines A & B H^∞ MTBF MTTR PM

Cell 2 Machines C & D MTBF MTTR PM

Cell 3 Machine E No MTBF No MTTR PM

For Run #7 through Run #10, repeat Runs #3 through Run #6 by having setup’s for Machine E as specified in Table 4 (Set-Up Times Map for Machine E) with “Constant release of one (1) lot (48 wafers/lot) every 120 minutes”.

Table 2. Kempf Five Machine Six Buffer Mini-FAB Specification

Number of Machine Groups	3
Semiconductor Operations	Diffusion	Implant	Photo
Manufacturing Cells	Cell 1	Cell 2	Cell 3
No. of Machines/Group	2	2	1
Number of Job Types	3
Number of Tasks/Job	6	6	6
Job Types (products)	Pa	Pb	TW
Distribution Function of Job Types	0.60	0.36	0.04
Constant Mean Inter-arrival Time of Jobs	2 hrs.	120 mins.
Length of the Simulation	730 days	17120 hrs.	1051200 mins.
Ramp-Up Bias	182.5 days	4380 hrs.	262800 mins.
Number of Shifts per Day	2 shifts	12 hrs. each
Lot Size - wafers	48
Start Buffer	Infinity
Controllers	PID	H^∞
Schedulers	FIFO	MIVP®

Table 3. Cell Layout

Start	starts in warehouse	far left end	buffer = infinite
C1	Ma & Mb	left	buffer max = 18 lots
C3	Me	center	buffer max = 12 lots
C2	Mc & Mb	right	buffer max = 12 lots
Out	outs to warehouse	far right	buffer = infinite

Table 4. Production management for 3 products

Process Flow and Machine Groups in Route

Job Type	S1	S2	S3	S4	S5	S6	out
Pa in	1	2	3	2	1	3	out
Pb in	1	2	3	2	1	3	out
TW in	1	2	3	2	1	3	out

Product Production Flow

Job Type	S1	S2	S3	S4	S5	S6	out
Cells	C1	C2	C3	C2	C1	C3	out
Machines	Ma	Mc	Me	Mc	Ma	Me	out
Machines	Mb	Md		Md	Mb		out

Mean Service Time (in minutes) for successive tasks

Job Type	S1	S2	S3	S4	S5	S6
Pa	225	30	55	50	255	10
Pb	225	30	55	50	255	10
TW	225	30	55	50	255	10

Mean Load Time (in minutes) for successive tasks

Job Type	S1	S2	S3	S4	S5	S6
Pa	20	15	10	15	20	10
Pb	20	15	10	15	20	10
TW	20	15	10