INTRODUCTION
This paper describes some
problems and investigations encountered when implementing new resource
scheduling and product release policies in a large semiconductor manufacturing
facility (FAB). Improving manufacturing by small incrementals over time based
on extensive experience can be beneficial. An increase in production as small
as 1% can potentially result in increased sales of $200,000 to $300,000 or more
per month in semiconductor manufacturing. The reverse for a bad decision.
Changing normal strategies in a successful FAB requires substantial supporting
evidence that the change will be successful. Reduction in cycle time through
new process resource scheduling and product release policies, can increase
productivity and improve yield. For example wafer yield is increased due to
less time available for contaminants by reducing the cycle time. New scheduling
and release strategies require extensive testing by simulations and actual
experiments on the shop floor before becoming accepted in practice.
The authors have used stochastic discrete event simulation
and partial implementation of Minimum Inventory Variability Scheduling and
Release Policies® (MIVSRP®) developed by ACADZ,
inc. in three semiconductor FABs with success [10].
The semiconductor industry has many definitions for priority
lots [14], [15]. A joint IBM, Siemens, and Toshiba study examines the impact of
hot lots on cycle time caused by priority lots [13]. In this FAB, five levels
of priority called MAXI’s are used with level one being the highest. A level
one priority lot receives a red tag and when it finishes a process on one
resource it is hand carried to the next resource in its process flow. The lot
does not wait in a queue for any resource. Therefore the total production
process time for this lot is very close to its theoretical best process time.
MIVSRP®’s
were introduced in this FAB in February 1996. The development of a simulation
model representing the FAB and a partial implementation of MIVSRP® were completed over the
period from May 1996 through October 1996.
This presentation describes briefly the theory behind MIVSRP®. Minimum inventory
variability resource scheduling and product release policies are also
discussed.
Finally a large semiconductor manufacturing facility is discussed
in generic terms, including (sanitized) data collection. The results of the
baseline output and historical data from this operating FAB using FIFO and DDF
are compared to MIVSRP®.
1 THEORY
1.1 Little’s
Law
Little’s law, or The Law of Inventory, in queueing theory [6]
states that:
where 
is inventory, 
is the mean arrival
rate of products for processing, 
is the total cycle
time, namely the total processing time plus the total waiting time involved. As
a result, for a fixed input or output, cycle time is proportional to the total
system inventory. For the same demand, the higher the inventory, the higher the
cycle time. The ability to use less inventory to meet the same demand is
paramount to being competitive in world markets.
We let 
be the average
service (processing) rate and 
be the server utilization
(loading intensity sometimes referred to as machine capacity), then
since
products are fed in no faster than the processing rate. Inventory turns per day
are used to measure productivity. Inventory turns equals average output per day
divided by the average inventory, so
1.2 Kingman’s Formula
To account for random variations in
arrival and processing times, let 
denote the
coefficient of variation of the inter-arrival times 
and let
denote the coefficient of variation of the service times 
. We define
is 
, the total system variability. Assume that the inter-arrival
times and service times are independent identically distributed (i.i.d.) random
variables and the two streams are independent of each other. Assume that there
is one server, so we consider a GI/GI/1 queue [8] (general independent service
times, and 1 server).
Kingman’s formula [7] states that
where,
= inventory
V = input variability + capacity variability 
= input rate /
processing rate 
1
or machine capacity
If is near 1, the
inventory is very sensitive to variability (see the equi-variability graph
below). For fixed system variability 
, the inventory decreases as decreases. For the
same demand, the smaller the variability, the lower the inventory. For the same
variability, the higher the loading, the higher the inventory. So reducing
inventory without improving the system can be detrimental.
We focus here on decreasing variability
to reduce cycle time 
and thereby reducing
inventory . At any given machine group, the service order of items in
the queue affects the variability of the output stream, especially so for
semiconductor fabrication processes because of resource sharing caused by
reentrant flows. These items may create larger or smaller variability in
inter-arrival times.
- Machine Capacity (Loading Intensity %)
With 
, we can obtain the theoretical cycle time. In this case, the
minimum inventory achieved is 
. From Little's Law, the minimum cycle time in this case is 
. But this is not possible for systems with 
. Let 
denote a stream of
inter-arrival times from an upstream machine and let 
denote the stream of
the service times for these arrivals. Let the inter-arrival times and the
service times be independent of each other. Let us schedule the upstream
machine. Since the arrival times and service times are independent, the best we
could hope to achieve through scheduling is to minimize variability for the
inter-arrival times.
So the task is to minimize the variability of the
inter-departure time of the upstream machine through proper scheduling of the
queue. If we introduce the correlation between the inter-arrival time and the
service time of the downstream machines, we get better results: if the random
variables and are correlated such
that 
, where 
>1 is a constant, 
, and 
..., 
[4], [5], [9], [10],
[11].
Hence, for a
system with uncertainty, we could achieve the same minimum inventory as the
deterministic system - the theoretical best!
Minimum Inventory Variability Scheduling and Release Policies® (MIVSRP®) developed by ACADZ,
inc. introduce maximum correlation between inter-arrival times and service
times to reduce the man-made scheduling and release variability.
1.3 Minimum
Inventory Variability Scheduling and Release Policies® (MIVSRP®)
With this policy, the dynamic inventory N(t) at time t, shown
in Figure 2., will keep close to the long-term historical average inventory 
(the profile) in a
stable factory. This leads to the reduction of the scheduling variability, reduction
in total inventory, and reduction in mean cycle time. The goal of MIVSRP® is the line balancing
to reduce WIP variability. Large queues in front of a particular resource will
cause irregularity in the process flow, i.e., an unbalanced line: some stations
are overloaded and some are starved. The mean cycle time will rise due to local
starvation even though the total system inventory stays approximately the same,
and it will rise due to the waiting time in the queue for those overloaded
processing stations [1], [2], [4], [5], [9], [10], [11]. MIVSRP® can reduce the line
imbalance by pulling WIP into the queues having lower inventory N(t) (at time
t) than the historical average inventory as shown in Figure 2.
Figure 2. WIP CHART [4], [5], [9], [10]
2 HEURISTICS
2.1 1-Step Ahead
MIVSRP®
We establish a priority list of operations:
Priority I: Operation 
such that
Priority II: Operation such that
and 
Priority III: Operation such that
Priority IV: Operation such that
and 
Where 
= These provide
decision rules: If Priority I does not exist, go to Priority II, if this does
not exist go to Priority III, and so on. If two items tie with the same
priority, use FIFO or DDF or some other (pre-defined) allocation rule. Once a
choice has been made, the wafer lot chosen is processed on the available
resource, here Machine A. This 1-Step Ahead decision set of rules is then
applied in parallel throughout the FAB. This tends to balance the total
production line.
For example, in Figure 2., four process steps require the
service of Machine A; Which process step do we choose? Machine A serving these
four process steps is the feeder machine to the next machine in the process
flow (called bleeder machine). Applying the priority rules from our 1-Step
Ahead MIVP® policy we look down
stream for all queues that have a job requiring the service of Machine A. A lot
is then selected from a queue in this set which will leave its instantaneous
queue length below its historical average, if a Priority I queue were
available. In our example, we would choose process step 35 which is of Priority
I, over the other three processes. If Priority I did not exist then we would
choose 10, (Priority II) which would avoid starving a potential bottleneck
machine. If Priority II did not exist, then we would choose 26, (Priority III).
Finally if Priority III did not exist we would choose 18, (Priority IV) which
increases the queue at the bleeder machine. Once we have made a choice we start
all over when Machine A becomes available. This example shows only four queues
in contention for service of Machine A, but in a reentrant line with multiple
products, there are many more. For example with ten products and ten reentrant
levels you could have up to one hundred queues. The following matrix Figure 3.
summarizes the selection order for any process resource, only the step numbers
for the queues change. This illustrates a 1-Step Ahead MIVP® scheme.
Figure 3. The Priority Matrix and the selection order for
Machine A in Fig. 1. [4], [5], [9], [10]
3 SEMICONDUCTOR FAB MODEL
3.1 Model
Definitions and Requirements
MIVSRP® is aimed at meeting
delivery schedules, reducing product cycle times, increasing product yield,
increasing product through-put, optimizing utilization of equipment resources,
increasing confidence for on-time delivery schedules, and increasing profits.
In the manufacturing world, companies use process resource schedules and
product release policies that are better than most, that agree with common
sense and can be implemented on the factory floor. Any improvements to resource
scheduling and product release policies must meet the above criteria and have
demonstrable success. We use stochastic discrete event simulation modeling to
test new scheduling and release policies. Our decision rules rely on common
sense and can be easily implemented by operators on a factory floor. The
control of process resource scheduling is refereed to as the inner loop
control, and the release of raw material into the factory is referred to as
outer loop control [12]. We will discuss the control of resource scheduling in
the remainder of this paper. MIVSRP® product release
policies will be discussed elsewhere.
Finding an optimal schedule for a given performance metric
within today’s semiconductor manufacturing is expensive in time and effort [3].
A reduction in the number of control variables is required to effectively use
what tools are available and to approach optimality within time constraints
available on a factory floor.
A global understanding of all the complexities involved in
wafer fabrication, starting with a raw wafer arrival through shipping the completed
product is required to improve scheduling and release policies. The reentrant
nature of certain critical resource tools, variations in recipes for processing
due to multiple products, and the random nature of machine failure and repair
introduce a higher level of complexity, and the number of variables is large. A
possible reduction in the number of key variables used to optimally control the
inner and outer loops should follow from analysis of a comprehensive simulation
model that has been validated in factories using historical data [16]. An
excellent discussion of the use of a reduced set of variables to maximize
decisions is presented in Ho [3].
The FAB Model must accurately represent the factory as a
production system. It must include the production mix, the production flows,
the production recipes and processing times, the equipment maintenance
database, and labor. An employee database is utilized when determining labor
requirements, but is not necessary when comparing product release and resource
scheduling policies. Correct staffing is important and does effect cycle time
and production but for our FAB Model and comparisons, staffing is assumed to be
equal and therefore it is not accounted for in the FAB Model when changing the
scheduling policies from FIFO and DDF to MIVSRP®.
The FAB Model compares a validated baseline simulation model
using FIFO, DDF and MAXI lots with one using new MIVSRP®. The development of the
baseline FAB Model is a long and tedious process, but if done with care and flexibility
for future updates, it will serve as an additional tool for management decision
making. Changes occur on a daily basis in a factory such as new product
introductions, new production flows, process changes reducing process steps,
changing process times on critical machines, and product elimination, just to
mention a few. A FAB Model must account for these changes. Changes, additions
and deletions must be easy to implement if management is going to support
simulation modeling in the future.
Given the complexity of a multiple product FAB and the
acceptance or non-acceptance of an outsider making any recommendations as to
how cycle time can be reduced. Communication cycle time reduction seminars were
given for section managers on a weekly basis. The MIVP® policies developed by
ACADZ, inc. and their results were discussed using previous research
simulations and implementation experience in two other FABs. Extend® Software was also
presented because of its visual icon-based libraries that could quickly represent
scenarios on the factory floor. At the same time, the FAB Model was formulated
with direct feedback from each of these
section managers. The team’s objective was to reduce cycle time to a set goal
of 29 days on average and 32 days with 95% confidence, prior to the end of the
3rd quarter. The 1-Step Ahead MIVSRP® was implemented on the
factory floor using the WIP Chart and Priority Matrix®. The MAXI priority
schedules were maintained because of commitment to certain customers but the
FIFO and DDF were changed to incorporate the 1-Step Ahead MIVSRP® priority scheduler for
resources. This was particularly useful when there were some major failures of
critical equipment. The production line was slowed down in front of these
resource failures and speeded up in front of other resources. When the
equipment came back on line the reverse was done for an amount of time equal to
the time that the equipment was down, thus maintaining a balanced line. The
following simulation examples show that the new scheduling methodology can
reduce the cycle time.
3.2 Research Results Using SEMATECH - Dataset #1
The original Dataset #1 received from SEMATECH in March 1995
(it was later revised in January 1996) included two non-volatile memory products
with two different process flows, 210 steps for product A and 245 steps for
product B. There were 85 machine groups (266 total machines) with historical
mean-time-before-failure (MTBF) and mean-time-to-repair (MTTR) data. There were
16,000 wafer starts per month with arrivals calculated on a constant
distribution. The actual (theoretical) raw process time for product A was 313.4
hours and 358.6 hours for product B. The start rate for product A was 380
wafers per day and 190.48 wafers per day for product B (revised in 1996). The
production lot size was 48 wafers. Our comparative results were generated by R.
Weidmeyer [11] using the discrete event simulation software package Extend®. He compared the ACADZ,
inc. 1-Step Ahead MIVSRP® resource scheduling to
FIFO with favorable results. A second comparison of the revised Dataset #1 was
been completed by V. Palmeri using the ACADZ, inc.’s K-Step Ahead MIVSRP®[17] (see this
conference). A Third comparison is being completed (August 1997) by T. Torsina.
He is comparing the ACADZ, inc.’s K-Step Ahead and J-Step Back MIVSRP®. These Studies used the
AutoMOD/AutoSCHED® simulation software.
3.3 Extend® SEMATECH
1-Step Ahead MIVSRP® Simulation Results
The Extend® Model was run to simulate
15,000 hours of continuous manufacturing with statistical data collected every
500 hours. The first 2,500 hours of data was eliminated due to ramp up of the
model. The goal was to establish a baseline model and collect data using FIFO
resource scheduling with the constant release policy and then compare this
baseline data with results collected for the 1-Step Ahead MIVSRP®. Work-in-progress and
cycle time statistical data were the two important sets of data that we were
interested in. The design of experiment was to collect 25 data points for
t-Test analysis for a paired two samples for a mean with a 95% confidence
interval test and an Analysis of Variance (ANOVA) for the simulation runs.
Table 1. below demonstrates, MIVP with a solid line, a reduction in variance
over the 25 data points while Table 2. below shows the average total queueing
time being reduced by 46% and 43% for the two products while using MIVPSRP®. The same constant
release policy was used for both simulations.
Table 1. SEMATECH Model Comparisons of FIFO with
1-Step Ahead MIVSRP®
Product
A Product B
Mean Cycle Time, FIFO 1,222.0 hrs. 1,551.0
hrs.
Mean Cycle Time, MIVSRP® 808.0 hrs. 1,043.0
hrs.
Raw processing Time 313.4 hrs. 358.6
hrs.
TQT, FIFO 908.6
hrs. 1192.4 hrs.
TQT, MIVSRP® 494.6 hrs. 684.4 hrs.
Reduction by MIVSRP® 414.0 hrs. 508.0
hrs.
Percentage
Improvement over FIFO 46% 43%
3.4 Motorola Model Statistics
This FAB produces a total of 73 different micro-controller
devices on 55 different production flows, each with processing steps ranging
from 185 to 395 steps (averaging 263 steps each). Ten of these products are on
the factory floor at any given time, involving 132 machine groups with a total
of 485 machines. The product can re-enter machine groups, such as Photo and
Etch, from six to fourteen times, depending on the device being fabricated.
Adding to this complexity the variability of MTBF, MTTR, including labor of 650
employees (labor was not modeled), and one can see that short interval
scheduling based on knowledge of the global process is important. Therefore,
the minimum number of variables is (10 technologies) times (10 average
products) times (263 average steps) times (132 machine groups) equals 3.47
million variables. Added to these MTBF and MTTR for each of the 485 machines
resulting in a very large number of variables for analysis. Rather we turned to
discrete event simulation.
Let us consider minimizing the total cycle-time (from raw
material to finished product) given a fixed input/output schedule. There are
three ways [18]: First, the process re-engineering of the steps in the process
flow, by possible elimination of a particular step or by improving the design
by what is known as engineering shrinks, i.e., getting more devices on the same
wafer. Second, the purchase of new equipment of the latest technology to
increase through-put. Third, is to minimize the cycle time by resource
scheduling, we try to reduce the wait time, the total queue time a product
spends waiting for service at all resources.
To minimize cycle time, one must reduce inventory or increase
capacity according to Little’s Law. If we extend this to Kingman’s formula, a
reduction of variability can also have an effect on cycle time and reduce
inventory. A balanced production line then is one if given a fixed input and
output schedule, the mean work-in-progress does not increase over time due to
randomness of machine failures and repairs. Section managers in a factory will
introduce a safety factor into their machine capacity numbers which takes into
consideration this randomness. They want to protect against this variability to
maintain a certain WIP and cycle time objective through their section of the
FAB. Introducing new scheduling policies which reduce cycle time and increase
capacity at the same time will meet with understandable resistance.
Unbalancing of a production line can be caused by
unpredictable disturbances such as equipment failures and repairs, personnel
decisions, power failures and, even bomb scares closing factories. These
disturbances disrupt the stable flow of products and may result in large queues
for some machines while other machines remain idle. Large queues, no matter
what the cause, are referred to as bottlenecks, and days or weeks might be
required to re-balance the production line when they occur. Bottlenecks cause
product to wait for service, thereby increasing its cycle time (CT). For our
discussion, cycle time is defined to be the sum of the total processing time
(TPT) and the total queueing time (TQT). TPT is defined as the sum of all the
raw processing times for each step in a production flow and TQT is defined as
the sum of all the queue waiting times for resource service for each step in a
production flow. A single piece of equipment often costs $1-2 million or more.
Particularly at reentrant operations many pieces of equipment may be required.
At these operations, a capital investment of $10-40 million is not unusual.
Millions of dollars can be spent on equipment to increase the capacity at a
critical bottleneck resulting in reduced cycle time locally, but the overall
cycle time of the product might not decrease. This local improvement approach
might simply move the bottleneck to another location along the manufacturing
line. Understanding that local changes to improve the service at overcrowded
machines generally will not improve the total product cycle time is of utmost
importance. Restarts, for example due to power failures or bomb scares are not
within the domain of this research.
Increased cycle time can mean delays in customer delivery,
lost sales, lost customers, and even monetary penalties. Long cycle times
compared to other suppliers is often a key factor in a competitor getting a
sale. Short, predictable cycle times are a competitive advantage. Short cycle
time also result in increase yield and a reduction of wafer scrap. Therefore we
search to reduce cycle time by reducing the man-made variability through
resource scheduling, product release policies, labor and machine utilization’s,
using historical MTBF and MTTR data.
3.5 FAB
Model Data Collection
Data collected for the
FAB Model included all the micro-controller devices manufactured in the past
two years. This included 34 shop orders (production flows) for 55 devices.
These are referred to as Product1, Product2. and Device1, Device2, etc. This
FAB’s production flow was broken down into distinct operations such as Photo,
Etch, Implant, Diffusion and Probe for the different metal layers on the device
and given specific code names. These operation code names Op1, Op2, etc., were
broken down into individual processing steps with actual process code names
(steps) which then could be managed by the process engineering teams for
process improvement, etc. These steps or process codes are referred to as Step1,
Step2, etc.). The 34 flows having a total of 1717 operations with individual
steps ranging from 2 to 15 depending on the operation giving a total of 8671
steps for all flows. Sanitizing the FAB Model data in this way by changing the
product (device names), the operation codes, and process step codes was
necessary to protect the proprietary nature of this facility.
3.6 Model
Design
The FAB Model logic was simplified for the production process
flow to cover multiple product process flows and to incorporate multiple
devices within a flow. The same device may have undergone engineering shrinks
over its life, starting with 16 devices per wafer, to today, with 132 devices
on the same wafer. The operations and actual steps within the production
process flow remains the same but the process time increases as the number of
devices per wafer increases. For example on certain tool sets such as the
steppers in photo. This is where the actual device circuit patterns for each
layer are photographically transferred through a photomask (reticle) onto a
wafer. To increase the potential devices per wafer causes an increase in the
number of exposures increasing the processing time per wafer. This total
process exposure time per device may not be a 1 to 1 correlation. If we take
the extreme case of a 1 to 1 correlation for a particular device as an example
and the exposure takes 10 seconds then it is easy to see 16 devices per 4 inch
wafer can take 160 seconds for old technology. After an engineering shrink of
this device has been accomplished to place 132 devices per 4 inch wafer the
exposure time can take 1320 seconds. This difference (1260 seconds) adds to the
cycle time of the product while the process flow remains the same. We use this
as example to demonstrate the need for look-up process timing tables for each
device. These tables were produced to take into consideration the engineering
improvements. We must point out that a calculation must be done for Cycle Time
per wafer and Cycle Time per device when determining the benefits of cycle time
reduction.
An Excel spreadsheet was created with the 34 different
product production flows as the column heading and the operation codes in order
of the flow as the row designation. It was found that 164 common operations
(out of a total of 1717 operations) was all that was required to cover the 34
production flows. Our FAB Model flow logic was decreased by 1047%. Table 2.
below shows how the operation flow logic was introduced into the FAB Model. The
flow for Product 1 would then be Operation 1, Operation 2, jump to Operation 5,
etc., and finally exit at Operation 164. All products then would visit
Operation 1 where the raw wafers are cleaned, receive a nitride deposit or an
initial oxidation and then laser scribed to identify the wafer for its life
through fabrication. They would then step through the flow sequence assigned by
Y being yes for an operation or by a blank meaning skip this operation. This
sequence of Y’s and Blank’s form the production flow logic of each device until
they exit at Operation 163 or Operation 164. Since the step sequence remained
the same for each operation, the only change therefore, would be in the process
times for certain tool sets, incorporating the process timing tables produced
for these critical steps. These look-up tables then can be easily updated as
new process innovations occur in the future.
Table 2. Production Flow Sequence
Examples
|
|
P1
|
P2
|
P3
|
P4
|
P5
|
P6
|
P7
|
*
|
*
|
*
|
P34
|
|
Op1
|
Y
|
Y
|
Y
|
Y
|
Y
|
Y
|
Y
|
*
|
*
|
*
|
Y
|
|
Op2
|
Y
|
Y
|
|
Y
|
|
Y
|
Y
|
*
|
*
|
*
|
|
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
*
|
|
OP163
|
|
Y
|
Y
|
Y
|
|
|
Y
|
*
|
*
|
*
|
Y
|
|
Op164
|
Y
|
|
|
|
Y
|
Y
|
|
*
|
*
|
*
|
|
The next database had to do with the equipment maintenance,
scheduled and unscheduled. This introduces the stochastic nature caused by
variability’s for MTBF and MTTR for the 485 machines used in production. By
interviewing each Section Manager, it was determined which machine groups did
single wafer processing, batch processing, and the minimums and maximums, i.e.,
wafer count for each processing step.
Next came the recipes and process times for each step on each
piece of equipment. Again the Excel spreadsheet proved invaluable. Each product
flow was entered with the column headings starting with the Product Flow ID (P1
- P34), Operation ID (Op1 - Op164), Step ID (S1 - S15), Process ID (Pr1 -
Pr700), Specification ID (Sp1 - Sp700), Equipment ID (E1 - E132), No. of Wafers
per process step (W#), Load Time in Minutes (LT), Unload Time in Minutes (UL),
Set-up Time in Minutes (ST), Cool Down Time in Minutes (CD), Wafer Travel Time
in Minutes (WT), Process Time per Wafer in Minutes (PTW or TW# for the Table
Number), Process Time per lot in Minutes (PTL or TL# for the Table Number),
Process Time per Batch in Minutes (PTB or TB# for the Table Number), Minimum
Batch Size (Bmin), Maximum Batch Size (Bmax), lot Scrap Probability (LS%),
Wafer Scrap Probability (WS%), Wafer Rework Probability (WR%), lot Scrap
Probability (LS%), Operation Rework Sequence (OpR#), and Operation Rework
Return To (Op#) along with some additional restraints and/or exceptions for
specific devices. Along the vertical axis, the row headings were actual process
sequence for each product flow, i.e., the individual process steps made up of
the 164 Operations and their individual steps. The total process steps in a
product flow ranged from 164 to 364 averaging 263 steps per product flow. This
table then had 289,443 entries but was created from the concept of only 164
different operations a combination of which were included for each product flow
taking advantage of the common operations.
Once the first Product Flow was created the next flow was a
copy of the first with skipped operations eliminated and the new operations
added, refer to Table 2. Repeating this copying and pasting until all the
Product flows were entered. This concept of copy and paste can allow for new
Product Flow introductions and/or deletions. Also when a new process change has
been tested and proven to be successful for one product, then it is a matter of
entering this change as a change all in the Excel spreadsheet and all Product
Flows are updated. This type of integrated database could possibly eliminate
some of the production errors on the shop floor caused by a new engineering
process change. In this FAB document control enters these changes one shop
order at a time. These manual changes are presently taking months to complete
in the FAB for all shop orders that could benefit from the change. We are at
this time investigating with Motorola
management how this database can be integrated to improve the cycle time on
production flow shop order changes.
We have created a master database for production. The next
item was to create the timing tables for each process step that required a
look-up table for the actual device that was being manufactured. These look-up
tables are Process Time per Wafer in Minutes (PTW or TW# for Table Number),
Process Time per lot in Minutes (PTL or TL# for Table Number), and Process Time
per Batch in Minutes (PTB or TB# for Table Number) mentioned above in our Excel
spreadsheet. This effort was completed by five graduate students (1 Post Doc, 3
graduate and 1 undergraduate all Motorola
employees) working closely with Dr. Collins as supervisor for ASU Independent
Study credit and each Section Manager. The specification database was first
researched to determine theoretical times for the different equipment sets and
then the students did stop watch time studies on the floor to confirm. This
effort took 500 person hours to collect, integrate into the FAB Model, and
validate.
The final step was the Probe Section in the FAB. The Probe
Section, sometimes referred to as Wafer Sort is the final staging of wafers
prior to shipment for final assembly. The wafers are laminated and/or
de-laminated, ground to a specified thickness, cleaned, dried, etc. Then each
die is probed to determine if the die meets specifications. Inking is done on
the die that fail the test. The wafers are then entered on the computer and
shipped. This step signals the Cycle Time Clock in the FAB Model for
statistics.
This section of the FAB required a complete timing database
taken from product specifications and the actual testing programs to be
incorporated in the FAB Model. Two students working with three Motorola engineers and the Probe Section Manager
built these timing tables for each device (also for academic credit). These
probe tests include the standardized test for electrical yield by Motorola and some additional probe tests required by
specific customers. There are 3 yield statistics that make up the fabrication
yield critical to semiconductor fabrication, wafer breakage (# wafers out/#
wafer starts), process variation and process defects (# good die/total die).
Yield is another concern in our MIVSRP® research.
With the FAB Database, the logic of the simulation model is
straight forward. First a generator is required to release the product devices
into the FAB. The summation of each device manufactured for the past two years
were calculated for each year. By knowing these sums for a 12 month period, we
then calculated the probability of arrival chart for each year. If this number,
for example, were 4800 wafers per week, the generator should generate a 48
wafer lot every 100.8 minutes with some distribution that represents past
history. For validation purposes we used a constant distribution for release of
raw wafer lots into the FAB. For actual simulated runs, we used a distribution
function which matches that of the actual quantity of products released into
the FAB over the last year.
We assigned several attributes to the lot for tracking
purposes in the FAB Model. First, a device number is assigned using historical
charts matching the probability of arrivals. An input random number generator
is used to create this probability table to identify the device number, D# from
1-73. Second, the operation number, Op#, and the step number, S# are
initialized to 1 for each lot arrival. These attributes are assigned to the
lots similar to a bar code. The only difference being the attribute values
change at each step and operation within the product flow.
The device number is first used in a Priority Number look-up
table to set the priority of the lot from 1 - 21, where smaller the number the
higher the priority. The device number is also used to select the production
flow, P#, from 1-55, from the Production Flow Number look-up table. This
priority attribute number and production flow number attribute is set for the
life of the lot and does not change. The wafer lot moves to a time clock (Cycle
Time Clock) where its arrival time is recorded. When the lot has completed all its
operations and steps and has been signed out after being probed and tested for
shipping, the time clock is signaled and the cycle time is recorded in a table
for this device. The average cycle time statistics for comparisons can be
produced over any period of time from this table.
Once the wafer lot leaves the time clock, it enters the first
operation. Each operation assigns additional attributes for the processing time
and/or look-up time table for each processing step. The operation also
determines whether or not this step is a batching step or a single wafer
process. If it is batching step the batch size is established. Each step within
an operation sends the wafer lot to the correct equipment tool set for
processing. If it is a batch process, the operator will often hold the lot
until the correct number of wafers have arrived before continuing. Once the
processing is complete the step number is incremented by 1 and the lot returns
to the operation for the next step. If it were a batched set of lots, the lots
are unbatched into the correct number of lots as previously batched and the
step number is incremented by 1 for each lot, the lot returns to the next step
number within the operation. When the lot completes all the processing steps
within an operation, the operation number is either incremented by 1 or by the
number required for the jumps in the flow (see Table 2.), and the step number
is reset to 1 for the next operation. When all the operations within a flow are
completed, the lot exits the FAB, and the time clock is notified of its
departure time.
When the lot arrives at an equipment set for processing, they
arrive into a priority queue. The lot attributes are checked to see if it is a
MAXI lot. Its value establishes its priority in the queue, the smaller the
number the higher the priority. Next the device number and/or operation number
are used to determine the processing time from a look-up table. If the process
is one where the device determines the processing time, then the device number
is used for a look-up table, otherwise the operation number is used. The lot
then moves to the next available equipment within the equipment set and is
processed. The maintenance database now comes into play and introduces the
stochastic nature of MTBF and MTTR which takes equipment down sometimes causing
product to wait in the queues. This wait time increases cycle time and its
reduction is one objective of the MIVP® research.
4 FAB MODEL STATUS AND FAB RESULTS
4.1 Fab Model Status
The validated FAB Model of the existing Motorola FAB was completed and turned over to Motorola in January 1997 by ACADZ, inc. The sanitized
version of the FAB Model is being used by ACADZ, inc. for continuous
improvement on the MIVSRP® algorithms using the historical
data of the previous two years of production. The sanitized version of the
model is also made available to Dr. Collins and his graduate students for
educational purposes and training.
4.2 FAB Implementation
Results
In this FAB, we developed a partial implementation of a
1-Step Ahead MIVSRP® policy, on the shop
floor under close supervision. When problems occurred in the FAB such as
equipment failures at the bottleneck sections, the operators were programmed to
look ahead and slow down the wafers that were headed for the downed machine
while speeding up the wafers that were headed for the up machines. The only
exceptions were the MAXI lots that were a very small percentage of the total
lots being produced.
The objective to reach 29 days average was accomplished and
even surpassed to 26.34 days. This represented a 29.7% reduction. The objective
of 32 days with 95% confidence was almost achieved (31.61 days), giving a 32.9%
reduction in cycle time. Over this same period wafer starts were decreased by
only 1.9%, wafers shipped increased by 2.3%, wafer yields increased by 0.15%,
and wafer scrap decreased by 23%. These positive results occurred in the period
from May 1996 through October 1996 (see Table 3. below).
Table 3. Motorola FAB
Implementation Results
5 SUMMARY
These heuristic agreements have been applied extensively in
the context of real factory production now in three FABs by [4], [5], [9],
[10], [11].
At Motorola we reviewed
MIVSRP®
and some of its problems and successes in implementing new scheduling
strategies in a large semiconductor manufacturing facility. We have
demonstrated the utility of using stochastic discrete-event simulation modeling
and control introduced here.
This research has been supported by, College of Technology
and Applied Sciences (ASU East), System Sciences and Engineering Research
Center (ASU Main) and by Motorola, Inc. Mesa,
AZ.
AutoMOD/AutoSCHED® is registered trademark of
AutoSimulations, Inc., all rights reserved.
Extend®
is registered trademark of Imagine That, Inc., all rights
reserved.
Minimum Inventory
Variability Scheduling and Release Policies®
, MIVSRP®,
1-Step Ahead MIVSRP®,
K-Step Ahead MIVSRP®,
K-Step Ahead and J-Step Back MIVSRP®,
MIVP®
are registered trademarks of ACADZ, inc., all rights reserved.
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